1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more specifically to a semiconductor integrated circuit including a fuse circuit.
2. Description of the Background Art
FIG. 3 is a block diagram showing an overall structure of a conventional semiconductor memory device. Referring to FIG. 3, the semiconductor memory device has normal operation and self refresh modes, and includes: a WE (Write Enable) buffer 1; a CAS (Column Address Strobe) buffer 3; a column address buffer 5; a column decoder 7 connected to column address buffer 5; an RAS (Row Address Strobe) buffer 9; a row address buffer 11 connected to RAS buffer 9; a row decoder 13 connected to row address buffer 11; a memory cell array 15; a sense amplifier 17; an I/O circuit 19 connected to sense amplifier 17; a self refresh switching circuit 21 an internal address generation circuit 23 connected to RAS buffer 9 and self refresh switching circuit 21 an address input terminal 20; a switch 22; and a refresh period determination circuit 25 connected to self refresh switching circuit 21.
Here, refresh period determination circuit 25 includes a ring oscillator 250 and a frequency divider 251 connected thereto.
Recently, with higher degree of integration and the speed of LSIs (Large Scale Integrations) including a dynamic random access memory (DRAM), a compact peripheral circuit portion is increasingly becoming an important factor to increase not only the degree of integration of a memory cell but also the space for the memory cell to occupy. In this context, interconnection pitch for the peripheral circuit portion is reduced. Therefore, it is a significant matter to reduce the number of defective products due to mis-blowing in the manufacture of fuse circuits adjusting periods such as refresh cycles by fuse blowing, And, to reduce the times of mis-blowing is effective for shortening the adjusting time.
FIG. 4 is a diagram showing a structure of the conventional frequency divider 251 shown in FIG. 3. Referring to FIG. 4, frequency divider 251 includes: a power supply node 30; a ground node 32; a counter 34; a counter 35 connected to counter 34; a counter 36 connected to counter 35; a fuse circuit 37 connected to counter 35; a fuse circuit 38 connected to counter 36; and an inverter 39.
Here, fuse circuit 37 includes: a high resistance element 371; a node n1; a fuse 372; and an N channel MOS transistor 373 having its gate supplied with a high level signal Sg. Fuse circuit 38 includes: a high resistance element 381; a node n2; a fuse 382; and an N channel MOS transistor 383.
Each of counters 34 to 36 outputs a signal with a period which is twice that of an input signal /CNTE when input signal /CNTE is activated to a low level, but directly outputs the input signal /CNTE when it is inactivated to a high level.
Thus, frequency divider 251 is structured such that a period of a signal REFSE output from frequency divider 251 is reduced by disconnecting fuses 372 and 382.
In other words, in an initial state in which both of fuses 372 and 382 are connected to the respective fuse circuits, N channel MOS transistors 373 and 383 included in fuse circuits 37 and 38 are on, so that signals /CNTE which have been activated to the low level are supplied for counters 35 and 36 from fuse circuits 37 and 38, respectively.
Then, both of counters 35 and 36 output signals with periods which are twice those of the input signals.
Here, assuming that only fuse 372 is disconnected, for example, signal /CNTE which has been inactivated to the high level is supplied for counter 35 from node n1 included in fuse circuit 37, so that counter 35 directly outputs an input signal OUT1 as a signal OUT2 with its period unchanged. Accordingly, when only fuse 372 is disconnected, signal REFSE is output from frequency divider 251 having a period which is one half that obtained when fuse circuit 372 is not disconnected.
It is noted that counter 34 never fails to output signal OUT1 with a period which is twice that of an input signal IN, and counters 34 to 36 are reset when an inverted signal RESET of a signal BBUE is activated to the high level.
In the above mentioned semiconductor memory device, however, the circuit is generally structured to afford a sufficient margin for a duration of a refresh period. Thus, the refresh period must be adjusted by disconnecting a fuse by laser blow. The operation of disconnecting by laser blow requires a prescribed time, and may disadvantageously produces defective circuits by mis-blowing.
An object of the present invention is to provide a semiconductor integrated circuit which allows reduction in the required disconnection times by laser blow in adjusting a refresh period to complete a good product.
According to one aspect of the present invention, the semiconductor integrated circuit includes: a first circuit; a second circuit connected to the first circuit; a first fuse circuit connected to the first circuit for generating a first activation signal activating the first circuit in the initial state and generating a first inactivation signal inactivating the first circuit when a first fuse included therein is disconnected; and a second fuse circuit connected to the second circuit for generating a second inactivation signal inactivating the second circuit in the initial state and generating a second activation signal activating the second circuit when a second fuse included therein is disconnected.
According to another aspect of the present invention, the semiconductor integrated circuit includes an oscillation circuit and an adjuster for increasing or decreasing oscillation frequency for the oscillation circuit by disconnecting at least one fuse.
Accordingly, an advantage of the present invention is to allow more efficient initial setting of the semiconductor integrated circuit by disconnecting the fuse.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.